ICS 155B
Computer Design Lab
Spring Quarter, 1998

Instructor Daniel D. Gajski
  218, ICS Engineering Research Facility

 

TAs

Andreas Gerstlauer (Email: gerstl@ics.uci.edu)

Shuqing Zhao (Email: szhao@ics.uci.edu)
  Office/Lab Hours: Wed Fri 10-12, CS 364

 

Lab

Undergraduate Sun Lab. CS364.

 
Design Tool Synopsys VHDL Compiler and Simulator

 

Prerequisites

ICS 151 and ICS 152

 

Primary Text

VHDL: Analysis and Modeling of Digital Systems
  Zainalabedin Navabi, McGraw-Hill, 1993

 

Useful References   

Principles of Digital Design
Daniel D. Gajski, Prentice Hall, 1997.

Structured Logic Design with VHDL
Armstrong James, Gray Gail, Prentice Hall, 1993.

VHDL: Hardware Description and Design
Roger Lipsett, Carl Schaefer, Cary Ussery
Kluwer Academic Publishers, 1989

 

1.
Required Material: All students should have access to ICS152 textbook: Principle of Digital Design, Daniel Gajski for refreshing their memory.

2.
Course Objective: In this course, you will simulate a digital processor or an ASIC by modeling it in VHDL. You will enhance the model by adding timing details and other design features. You will then analyze these model by executing certain benchmarks to obtain performance results.

3.
Tentative Lab Outlines: The lab portion of this course consists of 4 or 5 assignments. Each assignment involves the design, modeling and simulation of a module or feature of the digital processor or the ASIC. The first Lab is geared to increase your familiarity with the VHDL language and the tools you will be using. In the next few labs, you will be developing a complete design of datapath and controller of the processor or ASIC. You are also required to develop test vectors to simulate your design.

The lab format may change a little through the quarter. However, you should plan or spending approximately 10 hours a week in the lab. You can often reduce the time spent in the lab by doing your designs before coming to the lab. If the lab gets crowded and students have trouble accessing the machines, we will use sign-up sheets for scheduling use of the lab.

4.
Course Schedule: During the class lectures, we will discuss the lab assignments and review some basic principles relating to the lab assignments.

The lectures serve primarily as a guide to the labs. Their primary objective is to discuss lab assignment and to review material. All announcements will be made at the beginning of the class. It is your responsibility to come to class and not to miss the announcements.

5.
Grading: Since this is a lab course, your grade will depend primarily upon your performance in lab assignments that are completed on time.

You will be required to demo your simulation run to the TA during the TA office/lab hours. The TA will run several test cases on your design, so make sure that you have tested your design completely before you are ready to demo it. Your grade will depend on the number of test cases that perform satisfactorily on your model. Your final grade will be based on your cumulative performance on the lab assignments and the final completion of the processor or ASIC.

6.
Late Policy: No late assignments will be accepted. It is your responsibility to schedule your time around interviews etc. that you may have to go for. We will be handing out lab assignments well in advance, so there should be no excuse for late work. In the case of extenuating circumstances, see the instructor.

7.
Drop Policy: Students will not be allowed to drop the course after the seventh week of instruction.

8.
Lab Policy: No students may modify the system software on the workstations in any way. Students caught modifying the software will be subject to discipline as outlined for malicious conduct in the university regulations.

Any students caught putting a program containing a virus on any computer will be subject to discipline as outlined for malicious conduct in the university regulations.

Theft of software from the systems is subject to course expulsion and possible criminal charges.

9.
Lab Guidelines: Always design your system on paper and think of your modelling strategy before writing the VHDL code. This saves time and lets others use the computers more productively.

Organize your design as library directories, so that they can be used in later assignments.

Make sure that your design submissions have your name, ID#, the date written on them.

You may be required to give a demo of a completed lab assignments to the TA. In addition, most lab assignments require a short write-up. Details will be provided in the lab handouts.

Each students should read the bulletin board, ics.155b, for announcements etc. Students are responsible for reading this bulletin board as lab discussions, corrections and modifications will be posted there outside of class meetings.

Schedule for the Quarter

Lab # Handed out
(in class)
Lab Due on
(by noon)
Lab 0 April 6 April 13
Lab 1 April 13 April 20
Lab 2 April 20 May 4
Lab 3 May 4 May 18
Lab 4 May 18 June 1
Lab 5 June 1 June 15


Andreas Gerstlauer
1998-04-07